The present application relates generally to the manufacture of semiconductor devices, and more specifically to a multi-patterning method for forming polysilicon gate arrays.
Microelectronic circuit fabrication involves a series of photolithography masking steps for patterning of device structures. In advanced logic circuits and DRAM architectures, for example, fabrication process complexity can include more than one critical mask per level. However, minimization of critical masks is desired for manufacturing cost control.
Sidewall spacer double patterning or self-aligned double patterning (SADP) is a recently-developed paradigm for lithographic roadmaps. Rather than using lithography as the principal method for generating device features, however, the role of lithography is the generation of a mandrel (i.e., a pre-pattern) that will form the basis for subsequently formed patterns with varying degrees of density multiplication.
Disadvantageously associated with mandrel-based pattern definition of an array of features are defects related to the end-of-the-line disruption in the repeat symmetry of the array, i.e., isolated narrow features at the end of the line. Accordingly, it would advantageous to develop a double patterning method and associated structures that reduce the number of critical mask steps while eliminating the formation of defects and defect-inducing features at array ends.